Continuing advances in miniaturization and densification of integrated circuits have led to smaller areas available for devices such as transistors and capacitors. For example, in semiconductor manufacturing of a memory array for a dynamic random access memory (DRAM), each memory cell comprises a capacitor and a transistor. With shrinkage of the cell size, maintaining a sufficient amount of cell charge storage capacitance becomes a challenge in DRAM.
To increase capacitance, the semiconductor industry has moved from planar capacitor structures (e.g., “parallel plate capacitors”) to vertical capacitor structures known as “container capacitors”. Several techniques have been developed to fabricate such capacitors. One such technique includes fabricating a cup-shaped bottom electrode defining an interior surface and an exterior surface formed on a substrate. A recess between adjacent bottom electrodes is formed in the insulating layer to expose a portion of the electrodes' exterior surfaces. A capacitor dielectric and then a top electrode are deposited over the interior of the cup-shaped bottom electrode and the interior of the recess. Such a double-sided bottom electrode provides additional capacitance.
Conventionally, the bottom electrode of the double-sided electrode is formed of N-type hemispherical silicon grain (HSG). Using a double-sided HSG bottom electrode provides a higher surface area for increased capacitance. Current techniques to form the double-sided HSG bottom electrode include a selective HSG process and a combo HSG process. The selective HSG process requires selectively growing the HSG on the interior container surface and this results in an outside smooth and inside rough HSG electrode.
Poor selectivity of HSG growth results in HSG outgrowth on the exterior electrode surface, and this can cause cell-to-cell shorts, requiring the space between containers to be enlarged. The combo HSG process requires etching back the substrate using a hydrofluoric acid (HF) solution to expose a portion of the bottom electrodes outer surface. However, while etching back the substrate using the HF solution any pinholes present in the bottom electrode can cause locally preferential overetch and generate sinkholes and stringer problems in the substrate material. Further, the cell dielectric leakage increases due to the formation of high electric fields around sharp points due to a higher surface roughness of the HSG formed on the interior surface of the container. This results in a lower capacitance in the cell. Furthermore, current process flow to form the dual-sided HSG container exposes the formed HSG electrodes on a wafer surface to HSG floaters falling on the wafer and conductive surface defects that can cause cell-to-cell short.
Thus, there is a need in the art for a technique to form double-sided HSG electrodes that overcomes the above-described problems.